[CONTRACT] ASIC Design & Verification Engineer
, , Belgium
€ 80.000 - 100.000
Job Description
Job Title: ASIC Design & Verification Engineer
Job Type: Contract
Duration: 6-12 months' initial + chance to extend
Location: Belgium/Remote
Start: ASAP
Responsibilities
- Integrate legacy control and data path designs in new products
- Update and verify legacy designs to fit new product requirements
- Design and verify new ultra-high speed DSP blocks for next gen products
- Interface with the physical implementation team for further design and flow improvements
Required Experience
- Solid grasp of simulation concepts such as regression testing, UVM, functional coverage, assertions, …
- Good knowledge of Verilog and SystemVerilog for design and verification
- Experience with RTL lint
- Knowledgeable about DFT and ATPG
- Knowledgeable about CDC issues and techniques for low power design
- Experience with delay annotated gatelevel simulation
- Experience with implementation of high-speed pipelined FIR DSP structures is a plus
- Formal Verification experience is a plus
- Formal lint
- Sequential Equivalence Checking
- Assertion Based Verification
- Experience with C/C++/SystemC models for RTL verification a must
- Python and TCL programming experience a strong plus
- Able to efficiently work in a Linux command line environment as well as in Windows MS Office for reporting and documentation
Job Reference 19003TJP
Location Belgium - Flemish Brabant
Categorisation Digital IC Design / Verification: Verification
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